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SPIF223A
ATA to Serial ATA Bi-direction Bridge
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MAY 29, 2006 Version 1.2
Sunplus Technology reserves the right to change this documentation without prior notice. Information provided by Sunplus Technology is believed to be accurate and reliable. However, Sunplus Technology makes no warranty for any errors which may appear in this document. Contact Sunplus Technology to No responsibility is assumed by Sunplus Technology for any infringement of patent obtain the latest version of device specifications before placing your order.
or other rights of third parties which may result from its use. In addition, Sunplus products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
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SPIF223A
Table of Contents
PAGE
1. GENERAL DESCRIPTION .......................................................................................................................................................................... 3 2. FEATURES.................................................................................................................................................................................................. 3 3. REFERENCES ............................................................................................................................................................................................ 3 4. FUNCTIONAL BLOCK DIAGRAM .............................................................................................................................................................. 4 5. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 5 5.1. PIN DESCRIPTIONS ................................................................................................................................................................................ 5 5.2. PIN LIST ................................................................................................................................................................................................ 5 5.3. ATA INTERFACE REVERSE ...................................................................................................................................................................... 6 5.4. SPIF223A PIN DIAGRAM........................................................................................................................................................................ 9 6. ELECTRONICAL SPECIFICATION .......................................................................................................................................................... 10 6.1. POWER REQUIREMENT ........................................................................................................................................................................ 10 6.2. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 10 6.3. RECOMMENDED/TYPICAL OPERATING CONDITIONS ............................................................................................................................... 10 6.4. DC CHARACTERISTICS..........................................................................................................................................................................11 6.5. SPIF223A UART AND SPI INTERFACE SELECT: .....................................................................................................................................11 6.6. SPIF223A DEVICE MODE OR HOST : .....................................................................................................................................................11 6.7. SPIF223A ATA DEVICE MODE SELECT: .................................................................................................................................................11 6.8. SPIF223A SERIAL ATA BUS TRI-STATE FEATURE:...................................................................................................................................11 6.9. SPIF223A ATA BUS TRI-STATE FEATURE: ..............................................................................................................................................11 7. COMMAND LIST ....................................................................................................................................................................................... 12 7.1. ATA COMMAND LIST:............................................................................................................................................................................ 12 7.2. ATAPI COMMAND LIST: ........................................................................................................................................................................ 15 8. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 17 8.1. PACKAGE INFORMATION ....................................................................................................................................................................... 17 8.1.1. 64 pin TQFP............................................................................................................................................................................ 17 8.2. ORDERING INFORMATION ..................................................................................................................................................................... 19 8.3. STORAGE CONDITION AND PERIOD FOR PACKAGE ................................................................................................................................. 19 8.4. RECOMMENDED SMT TEMPERATURE PROFILE...................................................................................................................................... 19 9. DISCLAIMER............................................................................................................................................................................................. 20 10. REVISION HISTORY ................................................................................................................................................................................. 21
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SPIF223A
A SINGLE-CHIP SOLUTION FOR AN ATA TO SERIAL ATA DEVICE BRIDGE
1. GENERAL DESCRIPTION
The Sunplus SPIF223A is a single-chip solution for bi-direction of ATA to Serial ATA and Serial ATA to ATA device bridge. It could accept ATA commands through both ATA and SATA interface , decode the commands and converts them into ATA commands to the device. Response from the device through the serial ATA or ATA bus are deciphered, processed and converted to ATA protocol and sent to the host. The SPIF223A supports the Serial ATA generation 1 transfer rate of 1.5Gb/s (150MB/s) on the serial side and is compatible with Ultra133 on the ATA side. Serial ATA Features Integrated Serial ATA Link and PHY logic. Compliant with Serial ATA 1.0A specifications. Support Serial ATA Generation 1 transfer rate of 1.5Gb/s. Support Spread Spectrum in receiver. Support Serial ATA power saving Slumber.. ATA Features Compliant with ATA specifications. Compatible with Ultra ATA 133. Support PIO mode 0,1,2,3,4,5,6 MDMA0,1,2 and Ultra DMA mode : Partial, and
2. FEATURES
Overall Features Bi-Direction of ATA to Serial ATA bridge chip. Compliant with ATA specification. Compliant with SATA 1.0a specification. Compatible with Ultra ATA 133. Fabricated in 0.16um CMOS process with 1.8 volt core and 3.3 volt I/Os. Available in a 64-pin TQFP package with e-Pad . PHY isolation debug mode Full scan for high production test coverage Build-in 8051 uP to control data flow. Support UART, SPI, I2C bus. Support ATA bus skew-rate programming by UART/SPI interface.
2 1
mode 0,1,2,3,4,5,6 Support UDMA data transfer rates of up to 133MBps. Support ATA device master/slave/Chip select Support ATA bus timing control. Support ATA and ATAPI device like HDD and ODD, Tape.. Support ATA interface reverse feature. emulation.
3. REFERENCES
For more details about Serial ATA and ATA technology please refer to the following industry specifications: Serial ATA / High Speed Serialized ATA Attachment specification, Revision 1.0A. Http://www.T13.org/ ATA/ATAPI specifications.
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1
For e-Pad of SPIF223A, please always connect e-Pad to the For ATA bus timing control, please check with agent to get more
ground of application board.
2
information for UART/SPI interface.
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4. FUNCTIONAL BLOCK DIAGRAM
TestControlSignals SDAT SCLK
Test Controller I2C
PLL clock
XTALI XTALO
ATA
ATA IF
TX+/FIFO Registers Transport LINK SDIF PHY RX+/-
8051 RAM ROM UART Power Management
UAI UAO
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5.SIGNAL DESCRIPTIONS
5.1. Pin Descriptions
Table 5-1: Pin Types Pin Type I/O I O I-Sch P T Bi-directional Pin Input Pin with LVTTL Thresholds Output Pin Input Pin with Schmitt Trigger Pull-Down resistor is internal Tri-state Output Pin Pin Description
5.2. Pin List
Table 5-2: SPIF223A Pin Listing Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Pin Name B_IDE_DD[13] B_IDE_DD[2] B_IDE_DD[12] D3V3_IO B_IDE_DD[3] B_IDE_DD[11] B_IDE_DD[4] DVSS D1V8_CO B_IDE_DD[10] B_IDE_DD[5] B_IDE_DD[9] B_IDE_DD[6] B_IDE_DD[8] B_IDE_DD[7] I_IDE_RST_B RESET_B D3V3_IO IDE_ORD_INV CFG0 UART_SPI_SEL XTALI/CLKI XTALO VDDA GNDA REXT RXP RXN VDDA GNDA TXN Type I/O I/O I/O PWR I/O I/O I/O GND PWR I/O I/O I/O I/O I/O I/O I/O I PWR I I I I O PWR GND I I I PWR GND O ATA Interface Data Bus bit 13 ATA Interface Data Bus bit 2 ATA Interface Data Bus bit 12 3.3V Digital I/O Power ATA Interface Data Bus bit 3 ATA Interface Data Bus bit 11 ATA Interface Data Bus bit 4 Ground for the Digital Core and I/O 1.8V Digital CORE Power ATA Interface Data Bus bit 10 ATA Interface Data Bus bit 5 ATA Interface Data Bus bit 9 ATA Interface Data Bus bit 6 ATA Interface Data Bus bit 8 ATA Interface Data Bus bit 7 ATA Interface Reset. ASIC Reset input 3.3V Digital I/O Power ATA Cable Signal Ordering Inverse Device/Host mode enable UART/SPI interface enable 0: UART enable, 1: SPI enable Description
Crystal oscillator input or external clock input Crystal oscillator output 1.8V Analog Power Analog Ground External reference resistor input Differential receive +ve Differential receive -ve 1.8V Analog Power Analog Ground Differential transmit -ve
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Pin# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 TXP I_IDE_JUMP0 IDE_DASP IDE_JUMP1 TEST_CFG UAO_SPI_OUT SPI_En_B SPL_CLK UAI_SPI_IN D1V8_CO DVSS I2C_SDA D3V3_IO I2C_SCLK IDE_PDIAG IDE_CS1_B IDE_CS0_B IDE_DA2 IDE_DA0 IDE_DA1 IDE_CSEL IDE_INTRQ IDE_DMACK_B IDE_IORDY D3V3_IO DVSS IDE_DIOR_B IDE_DIOW_B IDE_DMARQ IDE_DD[15] IDE_DD[0] IDE_DD[14] IDE_DD[1] Pin Name Type O I I/O I I O O O I PWR GND I/O PWR I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PWR GND I/O I/O I/O I/O I/O I/O I/O Differential transmit +ve Jumper 0 ATA Interface Device Active or Slave(Device 1) Present Jumper 1 Test Configuration bit 0 UART/SPI data output SPI Enable SPI Clock UART/SPI data in 1.8V Digital CORE Power Ground for the Digital Core and I/O I2C Serial Data 3.3V Digital I/O Power I2C Serial Clock ATA Interface Passed Diagnostics ATA Interface Cable Assembly Type Identifier ATA Interface Chip Select 1 ATA Interface Chip Select 0 ATA Interface Device Address bit 2 ATA Interface Device Address bit 0 ATA Interface Device Address bit 1 ATA Interface Cable Select ATA Interface Interrupt Request ATA Interface DMA Acknowledge ATA Interface I/O Ready ATA Interface DMA Read during Ultra DMA data-out bursts ATA Interface Data Strobe during Ultra DMA data-in bursts 3.3V Digital I/O Power Ground for the Digital Core and I/O ATA Interface I/O Read ATA Interface DMA Ready during Ultra DMA data-in bursts ATA Interface Data Strobe during Ultra DMA data-out bursts ATA Interface I/O Write ATA Interface Stop during Ultra DMA data bursts ATA Interface DMA Request ATA Interface Data Bus bit 15 ATA Interface Data Bus bit 0 ATA Interface Data Bus bit 14 ATA Interface Data Bus bit 1 Description
5.3. ATA Interface Reverse
IDE_ORD_INV = 0 IDE_ORD_INV = 1 Pin Name IDE_DD[0] IDE_DD[15] IDE_DMARQ
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1 2 3 4 5 6 IDE_DD[13] IDE_DD[2] IDE_DD[12] D3V3_IO IDE_DD[3] IDE_DD[11]
Pin Name
IDE_DIOW_ IDE_DIOR_ 6
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SPIF223A
IDE_ORD_INV = 0 Pin# Pin Name IDE_ORD_INV = 1 Pin Name IDE_DMACK_
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 www..com 45 46 47 48 49 50 51
B_IDE_DD[4] DVSS D1V8_CO IDE_DD[10] IDE_DD[5] IDE_DD[9] IDE_DD[6] IDE_DD[8] IDE_DD[7] I_IDE_RST_B RESET_B D3V3_IO IDE_ORD_INV CFG0 UART_SPI_SEL XTALI/CLKI XTALO VDDA GNDA REXT RXP RXN VDDA GNDA TXN TXP I_IDE_JUMP0 IDE_DASP IDE_JUMP1 TEST_CFG UAO_SPI_OUT SPI_En_B SPL_CLK UAI_SPI_IN D1V8_CO DVSS I2C_SDA D3V3_IO I2C_SCLK IDE_PDIAG IDE_CS1_B IDE_CS0_B IDE_DA2 IDE_DA0 IDE_DA1
7
IDE_INTRQ IDE_CSEL IDE_DA1 IDE_DA0 IDE_DA2 IDE_CS0_ IDE_CS1_
IDE_RESET_ IDE_DD[7] IDE_DD[8] IDE_DD[6] IDE_DD[9]
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SPIF223A
IDE_ORD_INV = 0 Pin# Pin Name IDE_ORD_INV = 1 Pin Name IDE_DD[5] IDE_DD[10] IDE_DD[4]
52 53 54 55 56 57 58 59 60 61 62 63 64
IDE_CSEL IDE_INTRQ IDE_DMACK_B IDE_IORDY D3V3_IO DVSS IDE_DIOR_B IDE_DIOW_B IDE_DMARQ IDE_DD[15] IDE_DD[0] IDE_DD[14] IDE_DD[1]
IDE_DD[11] IDE_DD[3] IDE_DD[12] IDE_DD[2] IDE_DD[13] IDE_DD[1] IDE_DD[14]
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SPIF223A
5.4. SPIF223A Pin Diagram
U1
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
IDE_DD13/DD0 IDE_DD2/DD15 IDE_DD12/DRQ D3V3_IO IDE_DD3/DIOW# IDE_DD11/DIOR# IDE_DD4/DMAK# DVSS DIV8_CO IDE_DD10/IRQ IDE_DD5/CEL IDE_DD9/DA1 IDE_DD6/DA0 IDE_DD8/DA2 IDE_DD7/CS0# IDE_RST_B/CS1#
IDE_DA2/DD8 IDE_DA0/DD6 IDE_DA1/DD9 IDE_CSEL/DD5 IDE_INTRQ/DD10 IDE_DMACK_B/DD4 IDE_IORDY D3V3_IO DVSS IDE_DIOR_B/DD11 IDE_DIOW_B/DD3 IDE_DMARQ/DD12 IDE_DD15/DD2 IDE_DD0/DD13 IDE_DD14/DD1 IDE_DD1/DD14
IDE_CS0_B/DD7 IDE_CS1_B/RST# IDE_PDIAG I2C_SCL D3V3_IO I2C_SDA DVSS D1V8_CO UAI/SPI_IN SPI_CLK SPI_EN_B UAO/SPI_OUT TEST_CFG IDE_JUMP1 IDE_DASP IDE_JUMP0
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SPIF223A TQFP-64 pins
TXP TXN GNDA VDDA RXN RXP REXT GNDA VDDA XTALO XTALI/CLKI UART_SPI_SEL CFG0 IDE_ORD_INV D3V3_IO RESET_B
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TQFP_64 QFP64-0.5-SKT-A
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6.ELECTRONICAL SPECIFICATION
6.1. Power Requirement
Table 6-1: Total Power Dissipation Symbol IIO Ianalog Parameter Absolute digital I/O pad power supply Absolute digital power supply and PHY Condition Min. 3.3v 1.8v 0 60 Limits Typ. 5.0 90 Max. mA mA Unit
6.2. Absolute Maximum Ratings
Table 6-2: Absolute Maximum Ratings Symbol VIO Parameter Absolute digital I/O pad power supply voltage VCORE VASATA Absolute digital power supply Absolute analog power supply voltage for PHY VI TSTR Absolute input voltage Absolute storage temperature Condition Rating Min. 3.0 1.62 1.62 3.0 -40 Limits Typ. 3.3 1.8 1.8 3.3 25 Max. 3.6 1.98 1.98 3.6 150 V V V V Unit
6.3. Recommended/Typical Operating Conditions
Table 6-3: Recommended/Typical Operating Conditions Symbol VCORE VIO VASATA Parameter Operating digital power supply voltage Operating digital I/O pad supply voltage Operating analog power supply Condition Min. 1.62 3.0 1.62 3.0 0 Limits Typ. 1.8 3.3 1.8 3.3 25 Max. 1.98 3.6 1.98 3.6 70 V V V V Unit
voltage for SATA PHY VI TOPE Operating Input signal voltage Operating temperature
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SPIF223A
6.4. DC Characteristics
Table 6-4 DC Characteristics Symbol VIL VIH VT VT VT II IOZ RPU RPD VOL VOH IOL Parameter Input low voltage Input high voltage Threshold point Condition Min. -0.3 2.0 1.45 1.47 0.90 VI=5.5V or 0V VO=5.5V or 0V 46 30 IOL (min) IOH (min) VOL=0.4V VOL=0.4V IOH High level output current VOL=2.4V VOL=2.4V 4mA 8mA 8mA 12mA 2.4 4.5 8.9 12.3 18.5 Limits Typ. 1.59 1.50 0.94 70 58 6.6 13.2 24.8 37.1 Max. 0.8 VDDPST+0.3 1.77 1.50 0.96 10 10 114 129 0.4 8.3 16.7 40.5 60.8 V V V V V A A K K V V mA mA mA mA Unit
+ -
Schmitt trig. Low to High threshold point Schmitt trig. high to low threshold point Input leakage current Tri-state output leakage current Pull-up resistor Pull-down resistor Output low voltage Output high voltage Low level output current
6.5. SPIF223A UART and SPI Interface Select:
SPIF223A have supported 2 IO interface: UART and SPI. it could be configured by pin21 (UART_SPI_Sel) UART_SPI_Sel : 0 UART_SPI_Sel : 1 Using UART interface. Using SPI interface. Then,
Mode Master Slave Cable Select
IDE_JUMP0 0 1 1
IDE_JUMP1 0 0 1
6.6. SPIF223A Device Mode or Host :
SPIF223A have supported both dirction : SerialATA to ATA host bridge and ATA to SerialAT host bridge. Then, we could use pin20 (H_D_Sel). H_D_Sel : 0 H_D_Sel : 1 Serial ATA ATA device device to to Serial ATA host mode ATA host mode. (Connecting to ATA HDD).. (Connecting to Serial ATA HDD).
6.8. SPIF223A Serial ATA bus Tri-state Feature:
SPIF223A have supported Serial ATA bus Tri-state feature under UART_SPI_SEL as low. It could help to design a combo interface or multi-interface product. SPI_CLK : Low SPI_CLK : High Serial ATA bus Hi-Z. Serial ATA bus normal feature.
6.9. SPIF223A ATA bus Tri-state Feature:
SPIF223A have supported ATA bus tri-state by pin 38 (SPI_EN). If SPI_EN# is low, SPIF223A will enable ATA bus Tri-state. (For this mode, UART_SPI_Sel must be low.) ATA bus Tri-State ATA bus normal feature. If
6.7. SPIF223A ATA Device Mode Select:
When SPIF223A have been choice to H_D_Sel as 1, it will use as ATA device mode. For ATA device, SPIF223A could support master, slave and Cable select. It could be configured by : www..com
SPI_EN# is high, SPIF223A will go into normal function to accept ATA bus access. SPI_EN# : Low SPI_EN#: High
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7.COMMAND LIST
The SPIF223A ATA to Serial ATA Controller decodes ATA commands in hardware. The commands supported include ATA/ATAPI-5 and ATA/ATAPI-6 commands, including the 48-bit LBA extended commands. Certain obsolesced commands are also supported. The supported commands are listed below:
7.1. ATA Command List:
Table 7-1 ATA Standard Commands
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SPIF223A
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7.2. ATAPI Command List:
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3
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3
About ATAPI command, SPIF223A will not support 16-byte SCSI command if ATAPI device don't indicate 16-byte packet support on
Identify packet device information.
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8.PACKAGE/PAD LOCATIONS
8.1. Package Information 8.1.1. 64 pin TQFP
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SPIF223A
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Fig 8-1: SPIF223A in TQFP-64 package E-Pad dimension could be changed without notice.
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SPIF223A
8.2. Ordering Information
Product Number SPIF223A - HF021 Package Type Green Package form - TQFP 64*
8.3. Storage Condition and Period for Package
Package TQFP Moisture sensitivity level LEVEL 3 Max. Reflow temperature 255 +5/-0 Floor life storage condition 168Hrs @ 30/ 60% R.H. Dry pack Yes
Note1: Please refer to IPC/JEDEC standard J-STD-020A and EIA JEDEC stand JFSD22-A112 Note2: or refer to the "CAUTION Note" on dry pack bag.
8.4. Recommended SMT Temperature Profile
This "Recommended" temperature profile is a rough guideline for SMT process reference. Most of SUNPLUS leadframe base product choice Matte Tin and Sn/Bi for plating recipe. For PPF(Pre-Plated Frame) product with 63/37 solder paste, we recommend 240~245 for peak temperature.
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SPIF223A
9.DISCLAIMER
The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF SUNPLUS reserves the right to halt production or alter the specifications and regarding the freedom of the described chip(s) from patent infringement. MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. prices at any time without notice. publication are current before placing orders.
Accordingly, the reader is cautioned to verify that the data sheets and other information in this Products described herein are intended for use in normal commercial applications. Please note that application circuits
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. illustrated in this document are for reference purposes only.
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10. REVISION HISTORY
Date MAY 29, 2006 Revision # 1.2 Description 1.Update application into datasheet . (UART/SPI, ATA_bus Tri-State, SerialATA Hi_Z) 2.Update AC timing 3.Add command list for ATA command and Packet command. APR. 25, 2006 1.1 1.Update application into datasheet . (UART/SPI, ATA_bus Tri-State, SerialATA Hi_Z) 2.Update AC timing 3.Add command list for ATA command and Packet command. 4.Update pin assignment, 5.Add ATA interface reverse 5.3 section. SEP. 08, 2005 1.0 Original Page 3-6 10-11 12-16 3-6 10-11 12-16 18 6-8 16
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